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| STLC1512 NorthenLiteTM G.lite Loop Driver PRODUCT PREVIEW s s s s s s s s s s s Low power architecture -- Class AB, current drive, output stage through a centre tapped transformer to facilitate power supply switching between 5.0V and a lower voltage. (3.3V in the reference design) This gives a reduction in power consumption. 480mW power consumption with a typical G.lite signal. 600mA current driving capability Positive +5.0V and one lower supply. (3.3V in the reference design) Switching power supplies to save power Thermal overload shutdown Four programmable receive gains Opamp for a low pass filter in the receive path Undedicated opamp with separate power down control (used as a transmit path filter in the reference design) Separate power down control for Tx and Rx path 48-pin TQFP (7x7x1.4mm) package TQFP48 (7x7x1.40) ORDERING NUMBER: STLC1512 1.0 GENERAL DESCRIPTION The STLC1512 G.lite line driver chip contains the line driver as well as part of the receive path required in a central office G.lite modem. It provides an interface between the AFE chip (STLC1511) and the telephone line. The line driver chip has been designed with low power consumption, high signal to noise plus distortion ratio and high current driving capability. Figure 1. Block Diagram DCFBON PAIN DCFBOP AMPIN AMPIP AMPOUT PAIP TXANG RBIAS REF2P5 RXANG RX REF Buffer LPF AMP TX REF Buffer Thermal Shutdown Preamp Power Stage OPAMP DC Feedback DCFBIP DCFBIN FPP PWRVEEx Amp PAOPx BUFFP BUFFN FPN PAONx BIAS RXPD AMPPD TXPD PGA LPFIN LPFOUT PGAIN PGA1 PGA0 PGAOUT November 2000 This is preliminary information on a new product now in development. Details are subject to change without notice. 1/26 STLC1512 1.0 GENERAL DESCRIPTION The line driver transmit path contains a preamplifier followed by a power output stage. The power stage has current outputs that directly drive the primary side of a center tapped transformer. The receive path contains a programmable gain amplifier followed by an opamp which is used with off chip passive components in an active low pass filter. The Programmable Grain Amplifier (PGA) has four steps optimized for the recommended G.lite CO line interface. There is also an undedicated opamp which can be used for active filtering in either the transmit or reFigure 2. STLC1512 pinout ceive paths 2.0 PACKAGING AND PIN INFORMATION 2.1 Package Technology STLC1512 will be packaged in a TQFP 48 package, according to JEDEC Specification reference MS026-BBC. 2.2 STLC1512 Pin Allocation The pin out for the STLC1512 is depicted in the following Figure 2. AMPOUT QVEETX TXVCC3 TXVCC2 TXVCC1 TXVEE1 TXVEE2 TXVEE3 DCFBIN DCFBIP AMPIN AMPIP DCFBON DCFBOP TXANG FPP FPN PAIP PAIN RBIAS REF2P5 NC LPFOUT LPFIN 48 1 QVEERX RXVEE1 RXVEE2 PGA1 PGA0 RXVCC2 RXVCC1 RXANG AMPPD PGAIN TXPD NC PWRVEE1 PWRVEE2 PAOP1 PAOP2 BUFFP TQFP48 (7x7x1.4mm) BUFFN PAON1 PAON2 PWRVEE3 PWRVEE4 RXPD 2/26 PGAOUT STLC1512 2.3 Pin Description The pin description for the STLC1512 is given in the following Table 1. Table 1. Pin Description Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Pin Name PGAOUT PGAIN RXANG RXVCC1 RXVCC2 QVEERX RXVEE1 RXVEE2 PGA0 PGA1 TXPD AMPPD2 RXPD PWRVEE4 PWRVEE3 PAON2 PAON1 BUFFN BUFFP PAOP2 PAOP1 PWRVEE2 PWRVEE1 NC DCFBIN DCFBIP QVEETX TXVEE3 TXVEE2 TXVEE1 TXVCC1 AI AI VEE VEE VEE VEE VCC Pin Type AO AI AO VCC VCC VEE VEE VEE DI DI DI DI DI VEE VEE AO AO AO AO AO AO VEE VEE Pin Description1 Rx PGA output (programmable gain amplifier) Rx PGA input 2.5V Rx buffered reference +5.0V supply for Rx path circuitry +5.0V supply for Rx path circuitry Quiet ground for the Rx circuitry Ground for Rx path circuitry Ground for Rx path circuitry PGA gain setting control bit 0 PGA gain setting control bit 1 Tx path power down control (Active low) Undedicated opamp power down control (Active low) Rx path power down control (Active low) Power stage ground. Power stage ground. Tx Power Amplifier Negative output Tx Power Amplifier Negative output Current generator buffer negative output Current generator buffer positive output Tx Power Amplifier Positive output Tx Power Amplifier Positive output Power stage ground. Power stage ground. Not connected Power amp DC feedback amplifier negative input Power amp DC feedback amplifier positive input Quiet ground for Tx circuitry Ground for Tx path circuitry Ground for Tx path circuitry Ground for Tx path circuitry +5.0V supply for power amp output stage 3/26 STLC1512 Table 1. Pin Description 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 TXVCC2 TXVCC3 AMPOUT AMPIN AMPIP DCFBON DCFBOP TXANG FPP FPN PAIP PAIN RBIAS REF2P5 NC LPFOUT LPFIN AO AI VCC VCC AO AI AI AO AO AO AO AO AI AI AO AI +5.0V supply for power amp output stage +5.0V supply for Tx path circuitry and bias blocks Undedicated opamp output Undedicated opamp negative input Undedicated opamp positive input Power amp DC feedback amplifier negative output Power amp DC feedback amplifier positive output 2.5V Tx buffered reference Fast path positive output Fast path negative output Tx Power amplifier positive input Tx Power amplifier negative input Reference resistor generating bias current Externally supplied 2.5V reference Not connected LPF (low pass filter) Op Amp output LPF (low pass filter) Op Amp negative input <1>The values of the components that are connected to the pins are shown in Figure 11. <2>If the undedicated opamp is used in the transmit path, AMPPD can be connected to TXPD on the board. If the undedicated opamp is used in the receive path, AMPPD can be connected to RXPD on the board. This opamp is powered off of TXVCC3. 3.0 FUNCTIONAL DESCRIPTION The STLC1512 consists of the following functional blocks: s Transmit Signal Path s s Receive Signal Path Thermal Protection The receive path consists of a Programmable Gain Amplifier (PGA) and an active low pass filter. The PGA is programmable in four steps. The active low pass filter is composed of an on chip op amp and external passive components. The receive signal passes through the PGA, is low pass filtered and then driven off chip to the AFE chip. Both the PGA and the opamp can be powered down by RXPD signal. A thermal protection circuit has also been implemented on the chip to prevent the chip from overheating under fault conditions. 4.0 SPECIFICATIONS 4.1 Chip Specifications The cross-talk specifications are based on the assumption that cross-talk should not degrade the SNDR of the receive signal. If there is receive crosstalk into the transmit path, this signal will come back through the hybrid balance and cause noise in the receive path. If the signal is undistorted it will cause a small gain and phase error which will not affect performance. If it is distorted it will cause an increased The transmit signal that comes from the AFE is filtered before it reaches the line driver. STLC1512 contains an opamp that can be utilized as part of this filter. The AMPPD pin allows this op amp to be powered down independently. The line driver consists of a preamp followed by a current drive power stage. The preamplifier provides large open loop gain while the power stage provides open collector current drive to allow for single supply switching. The center tap of the primary side of the transformer is connected to a supply that can be switched between 5.0V and a lower supply to realize power savings on a DMT signal. The reference design sets this supply at 3.3V. The line driver can be powered down by a low at the TXPD pin. 4/26 STLC1512 noise floor which will degrade the SNDR of the receive signal. The same is true of the transmit signal. If the signal is undistorted it will show up out of band in the receive path and will not degrade SNDR. However, if the Table 2. Chip Performance Specifications Description Rx Cross-Talk into Tx Undistorted Rx Cross-Talk into Tx Distorted Tx Cross-talk into Rx Undistorted min nom max -55 Units dB Comments Measured from the active low pass filter output in the receive path to tip and ring. Measured from the active low pass filter output in the receive path to tip and ring. Measured from tip and ring to the active low pass filter output with the maximum gain setting in place. Measured from tip and ring to the active low pass filter output with the maximum gain setting in place. transmit signal is distorted by the cross-talk mechanism it will show up in the receive band and could reduce the SNDR. The cross-talk numbers are specified from output to output under maximum gain conditions. -73 dB -50 dB Tx Cross-talk into Rx Distorted -86 dB 4.2 Power Amplifier Performance Specifications The power amplifier must be specified with all of the external components in the application diagram. Without these components the amplifier will not function correctly. Specifications that are measured at the chip are specified as such in the comments. Table 3 contains the conditions over which the specifications in Table 4 apply. The limits on the specifications in Table are valid over all of the ranges specified in Table 3. The nominal values of the specification occur at the nominal value of all of the conditions in Table 3 unless otherwise specified. ... Table 3. Power Amplifier Performance Limits Description Gain Ambient Temperature Line Impedance min 19.9 -40 80 nom 20.1 27 100 max 20.3 85 160 Units dB oC Comments1,2 W A nominal chip will have no problem driving 200 or 50 . Supply voltage for TXVCC 4.75 5.0 5.25 V <1>Nominal specifications are for nominal bias and process <2>Maximum and minimum specifications are for worst case process and bias conditions 5/26 STLC1512 Table 4. Power Amplifier Performance Specifications Unless otherwise specified nom specs apply to the nom conditions in attribute and the max and min conditions are defined by the process and other spec limits that give these worst case corners. Description Quiescent current at PAOP/ PAON1 min 10 nom 15 max 18 Goal Units mA Comments The spec is measured as the sum of the currents at POAP1+PAOP2 or PAON1+PAON2. Measured at the center tap of the transformer. Measured at pin PAIP/PAIN. This parameter cannot be measured very accurately. Measured at pin PAOP1,2/ PAON1,2 Total quiescent current at output stage2 Input bias current3 20 30 36 mA 15 A Minimum Voltage at PAOP/ PAON 4 High Current Drive Minimum Voltage at PAOP/ PAON5 Low Current Drive Common mode input voltage range6 Peak output sink current on pin PAOP and PAON7 Power supply rejection Slew Rate8 Output referred noise voltage9 Signal to distortion ratio Two tone A10 Im2 @ 200 kHz Im3 @ 100 kHz Two tone B 0.85 Vpeak 0.70 Vpeak Measured at pin PAOP1,2/ PAON1,2 VCC0.5 1000 V Measured at pin PAIP/PAIN 600 mA This is the sum of the current from PAOP1 and PAOP2 or the sum of the currents from PAON1 and PAON2 See Figure 3. V/S Measured across the 100 Ohm line impedance measured at f=120kHz Simulated to be good from 30kHz to 540kHz. Measured at the line impedance. The 4 to 1 transformer must have total harmonic distortion better than 50dB over 30kHz < f < 550kHz. The multi-tone spec is the important spec. The two tone specs exist because the test equipment may not be able to create a good enough multitone input signal. 78 120 nV//Hz 78 78 59 78 59 85 66 86 86 59 86 59 dB dB dB dB dB 6/26 STLC1512 Table 4. Power Amplifier Performance Specifications Thermal shutdown junction temperature 12 <1> <2> <3> <4> <5> <6> <7> 130 150 175 oC Only the power amplifier is shut down under overheat condition <8> <9> The quiescent current is the current flowing into pin PAOP/PAON when there is no signal. This is the current drawn from the power supply that is connected to the center tap on the primary side of the transformer. This is the current flowing into the pin PAIN or PAIP when there is no signal. The nature of the test set up makes this quantity very difficult to measure. It is verified through simulation. This will allow the distortion specs to be met while driving a 160W line impedance. This applies for a 550mA output current. The worst case impedance for a nominal chip is 200 W. This spec is meant as an aid in calculating the proper switching point. It applies for a 225mA output current. This is a requirement on the input signal that allows the distortion spec to be met. It is not a testable parameter. The ran ge has been arrived at from simulations. The minimum sink current refers to peak signal current in normal operation. This is tested by placing a 80 W load as the lin e impedance and ensuring that the amplifier still passes the distortion tests. The maximum sink current refers to the current tha t will be delivered if tip and ring are shorted. A nominal chip can drive a 50W load while a worst case chip will drive 80W. Slew Rate spec is to guarantee that there is no slewing limit on a maximum amplitude sine wave at 540kHz. A 100 mV step is placed at the power amp input and the slew rate at the output of the amplifier is measured across the 100 Ohm load impedance. Measured across the 100 Ohm line impedance. This noise spec can be converted to dB/Hz through the following formula, e n x1000 N dB = 10 log ------------------------100 The effect of the noise in the receive path can be obtained by subtracting the hybrid balance number. <10> Two tone distortion is measured with two sine waves with each sine wave at an amplitude of 1/2 full scale (for signal gain of 20.1dB, the full scale signal at power amplifier input is 1.05 Vp). The two tone distortion requirement is measured from the rms voltage of a single signal tone to the rms voltage of the distortion product. For the Two Tone A spec the tones are at f1=500KHz and f2=300KHz giving Im2=200kHz and Im3=100kHz. For the Two tone B the tones are at f1= 500kHz and f2=450kHz so that Im3=550kHz. <11> A multi-tone sine wave is used for the DS (Down Stream) Multi-tone test. (The multi-tone signal will be 91 sine waves equally spaced from 35x4.3125kHz to 125x4.3125kHz with a peak-to-rms voltage ratio of 5.3 and an rms voltage equal to 208mV. Each tone will have a peak amplitude of 30.8mV) The multi-tone test measures the difference between the power of the test tones and the maximum power of a single distortion product in the given bands. <12> The thermal shut down can not be directly tested in production. It will be investigated at bench and a correlation will be done hermal shutdown temperature. 2 7/26 STLC1512 Figure 3. Power Supply Rejection of the Power Amplifier1 W DB (PAOUT) -40 -60 dB -80 -100 3.00e+04 1.00e+05 6.00e+05 Hz <1>This is a nominal specification. 6 dB of margin should be added to arrive at a worst case spec. 4.3 Programmable Gain Amplifier (PGA) Performance Specifications It should be noted that the PGA and LPF in the receive path must be AC coupled to avoid problems with amplifying any offsets. Both the PGA and the amplifiers are specified in terms of the silicon only. This is to allow the system design to be more flexible. The appendices show how to convert some of the silicon specs to system specs. Table 5. PGA performance Specifications Unless otherwise specified, NOM specifications apply for VCC=5.0V, temperature range outlined in Table 4.4, nominal process and bias current. MAX and MIN performances with 5% variation on VCC, -40 <= Tambient <=85oC, and worst case process and bias current and a minimum load of 440 W. DESCRIPTION Absolute Voltage Gain1,2 D=00 D=01 D=10 D=11 MIN NOM MAX UNITS COMMENTS Where `D' is the binary value of the control word [PGA1, PGA0] Gain settings are from the pin PGAIN to pin PGAOUT (See `application diagram') 11.4 1.4 -5.6 -19.8 11.8 1.8 -5.2 -19.2 12.2 2.2 -4.8 -18.8 dB dB dB dB 8/26 STLC1512 Table 5. PGA performance Specifications Relative Gain Accuracy2,3 11.8<--> 1.8dB step 1.8<--> -5.2 dB step -5.2 <--> -19.2 dB step Gain Variation with Temperature -0.15 -0.17 -0.2 -0.1 0 0 0 0 0.15 0.17 0.2 0.1 dB dB dB dB Assume a fixed Vcc, temperature, and frequency For a fixed Vcc and frequency (30kHz <=f<=120kHz) relative to 27o For a fixed frequency (30kHz <=f<=120kHz) and fixed temperature relative to Vcc=5.0V For a fixed Vcc and temperature relative to 30kHz Gain Variation with Supply Voltage -0.1 0 0.1 dB Gain Variation with Frequency 30KHz <= f <= 120Khz Signal to Distortion Ratio D=00 Two tone4 IM2 @ 200kHz IM3 @ 100kHz Output DS Multi-tone Echo5 30kHz<=f<=120kHz D=01 Two tone4 IM2 @ 200kHz IM3 @ 100kHz Output DS Multi-tone Echo5 30kHz<=f<=120kHz D=10 Two tone4 IM2 @ 200kHz IM3 @ 100kHz Output DS Multi-tone Echo5 30kHz<=f<=120kHz D=11 Two tone4 IM2 @ 200kHz IM3 @ 100kHz Output DS Multi-tone Echo5 30kHz<=f<=120kHz Input Referred Noise Voltage 6 at D=00 at D=01 at D=10 at D=11 -0.1 -0.001 dB Measured at pin PGAOUT for a minimum load impedance of 440 Ohm and maximum output signal of 1.1Vp. The important test is the multi tone test. The two tone specs exist because there may be a problem testing a multi tone wave. They will be correlated at bench. 86 86 86 dB dB dB 80 80 80 dB dB dB 76 76 76 dB dB dB 76 76 76 dB dB dB Measured at PGAOUT and referred to PGAIN. Tested at f=30kHz,120kHz,150kHz and 500kHz 5.8 11.6 22.5 95 7.5 15 30 133 nV/Hz nV/Hz nV/Hz nV/Hz 9/26 STLC1512 Table 5. PGA performance Specifications Input Impedance (over process) 7,8 Input Impedance (over temperature)7,9 Input Impedance (over process and temperature)7,10 Input Signal Level @ PGAIN Maximum Output Signal Level @ PGAOUT11 Power12 <1> <2> <3> <4> <5> 4.0 5 6.0 k Measure at pin PGAIN. For all PGA gains Measure at pin PGAIN. For all PGA gains Measure at pin PGAIN. For all PGA gains Single ended input Referenced to RXANG. For minimum load impedance of 440 Ohms. Active Power -10% 10% k 3.5 5 6.5 k 0 Vcc+0.1 1.1 V Vpeak 19 mW <6> The absolute gain test should be done at 30kHz, 75kHz and 120kHz with maximum output signal level of 1.1Vp. The calculation to show how to determine the gain from the line is given in Appendix A. This appendix also shows how to cal culate the gain variations in the application These are chip specs only. The application specs are calculated in Appendix A. Two tone distortion is measured with two sine waves having an amplitude given in 6. Tone one is at f1=500kHz and tone two is at f2=300kHz, IM2 appears at 200kHz and IM3 appears ar 100kHz. A multi-tone sine wave is used for the DS (Down Stream) Multi-tone test. (The multi-tone signal will be 91 sine waves equally spaced from 35x4.3125kHz to 125x4.3125kHz with a peak-to-rms ratio of 5.3 and an rms voltage given in Table 6. The multitone test measures the difference between the rms voltage of a single tone at the output to the rms voltage of the maximum distortion product at the output in the frequency band between 30kHz to 120kHz. This is the noise referred to the PGA input pin PGAIN. The input noise can be referenced to tip and ring in dBm/Hz through the formula, 100 2 N dB = 10 log ------------ V + G + H 1000 n where NdB is the line noise in dBm/Hz, Vn is the input referred voltage noise of the PGA, H is the hybrid loss (9.54dB) and G is the gain from the hybrid output to the input of the PGA. See Appendix A for calculation of G. Appendix B shows plots of the noise performance of the entire receive path as shown in Figure 9. <7> These numbers are required to determine the gain variations in the application. <8> The input impedance specified here is the nominal value and the variation is due only to processing. <9> The input impedance specified here is the nominal value and the variation is due only to temperature. This variation is specified from the nominal value at 27C. <10> The input impedance specified here is the nominal value with the variation due to both process and temperature. <11> This spec is guaranteed by the distortion test. <12> This power can not be verified independently. It can only be measured as part of the power from the RXVCC supply. Table 6. Multi-tone sine waves Gain Setting 00 01 10 11 2 Tone Amplitudes 173 mV 550 mV 1.125 V 1.125 V Multi-tone RMS 66 mV 207 mV 414 mV 414 mV Multi-Tone Amplitudes 9.78 mV 30.7 mV 61.4 mV 61.4 mV 10/26 STLC1512 Figure 4. Power Supply Rejection of the PGA1 dB <1>These curves represent typical performance. 6dB of margin is required for worst case. 4.4 Amplifier Performance Specification The two amplifiers on the STLC1512 are identical. One of them is used for the second order active low pass filter that follows the PGA in the receive path. The other is an undedicated opamp that can be used either in the transmit or receive paths. The LPF amplifier is powered from the RXVCC supply and is therefore intended to be used in the receive path. It has its positive terminal tied to the receive AC ground (RXANG) on chip. The undedicated op amp is powered from TXVCC. It is intended for use in the transmit path but could be used in the receive path. Using it in the receive path may cause receive noise to be coupled into the transmit path. There should not be an issue with transmit noise coupling into the receive path in either configuration. 11/26 STLC1512 Table 7. Amplifier Performance Specifications. Unless otherwise specified, NOM specifications apply for VCC=5V, temperature range outlined in Table 3, nominal process and bias current. MAX and MIN performances with 5% variation on VCC, -40 <= Tjunction <=115oC, and worst case process and bias current PARAMETER Input Offset Voltage Unity Gain Bandwidth Phase Margin Gain Margin DC open loop gain Slew Rate Signal to Distortion Ratio in negative unity gain1 Two Tone A2 IM2 @ 200 kHz IM3 @ 100 kHz Two Tone B3 IM3 @ 550 kHz Output DS Multi-tone4 30kHz<=f<=120kHz 150kHz<=f<=550kHz Signal to Distortion Ratio in positive unity gain. Undedicated opamp only.1,5 Two Tone A2 IM2 IM3 Two Tone B3 IM3 Output DS Multi-tone4 30kHz<=f<=120kHz 150kHz<=f<=550kHz Input referred voltage noise Input referred current noise 30 50 9 80 25 50 MIN NOM 5 MAX UNITS mV MHz degrees dB dB V / us Maximum output signal level=1.1Vp COMMENTS 89 89 59 dB dB dB The two tone B spec only applies to the undedicated opamp 89 59 dB dB Maximum output signal level=1.1Vp 78 78 59 78 59 dB dB dB dB dB 3.5 5 nV/Hz 2 pA/Hz <1>The multi tone spec is the spec which defines system performance. The two tone spec is available because it may not be possible to create an adequate multi-tone signal with the test hardware. <2>Two tone A distortion is measured with two sine waves with each sine wave at an amplitude of 1/2 full scale. Tone one is at f1=500kHz and tone two is at f2=300kHz. <3>Two tone B distortion is measured with two sine waves with each sine wave at an amplitude of 1/2 full scale. Tone one is at f1=500kHz and tone two is at f2=450kHz. 12/26 STLC1512 <4>A multi-tone sine wave is used for the DS (Down Stream) Multi-tone test. (The multi-tone signal will be 91 sine waves equally spaced from 35x4.3125kHz to 125x4.3125kHz with a peak-to-rms ratio of 5.3, an rms voltage equal to 207mV and a tone amplitude of 30.7mV.) The multi-tone test measures the difference between the rms voltage of a single tone at the output to the rms voltage of the maximum distortion product at the output in the band of interest. <5>The undedicated op amp specs are available in two configurations since it is undetermined which way the opamp will be used in the application. The distortion specs for the 2 configurations are very different. Figure 5. Circuit Connection for Measuring Distortion R R + Vin Vin Negative Unity Gain + Positive Unity Gain Figure 6. Power Supply Rejection of the Amplifier1 V D B (A M P O U T X) 10 0 -20 dB -40 -60 -80 1e+02 1e+05 1e+08 Hz <1>This curve is a nominal simulation. 6 dB of margin should be added for worst case. 13/26 STLC1512 4.5 Supply Rating and Operating Environment 4.5.1 Environment Conditions Table 8. Environment conditions PARAMETER Ambient Temperature Range (long-term) Ambient Temperature Range (Short-term)1 -40 to +80 -40 to +85 oC UNITS CONDITIONS C <1>Short-term is defined as no greater than 96 consecutive hours and 15 days per year 4.5.2 Maximum and Minimum Voltage Ratings Table 9. Maximum and Minimum Voltage Ratings PINS All Vcc pins All other pins Maximum 6.5V Vcc+0.4V Minimum -0.5V -0.4V 4.5.3 Power Supplies Table 10. Power Supply V/I (PIN NAMES) V(TXVCC1..2) V(TXVCC3) V(RXVCC1..2) V(PWRVEE1..4) V(TXVEE1..3)) V(RXVEE1..2)) P(TXVCC1..2) P(TXVCC1..2) P(TXVCC3) Description Supply voltage for Power Stage Supply voltage for TX Path Supply voltage for RX path Ground for PA Ground for Tx path Ground for Rx path Current drawn by TXVCC1..2 Current drawn by TXVCC1..2 Current drawn by TXVCC3 12.8 12 MIN 4.75 4.75 4.75 NOM 5.0 5.0 5.0 0 0 0 36.6 15.6 MAX 5.25 5.25 5.25 UNIT V V V V V V mArms mArms mArms While passing a full scale signal. 1 Quiescent Current While passing a full scale signal. P(TXVCC3) Current drawn by TXVCC3 7.5 9.2 mArms 14/26 STLC1512 Table 10. Power Supply P(RXVCC1..2) Current drawn by RXVCC 8.6 mArms While passing a full scale signal. P(RXVCC1..2) P(PAON/PAOP) Current drawn by RXVCC Current supplied through the center tap of the transformer. Current supplied through the center tap of the transformer. 6.6 93 8.4 mArms mArms P(PAON/PAOP) 20 36 mArms <1>The nominal power is all that is available for the active power because the power is very dependent on the line impedance. 4.5.4 Power Supply Noise Table 11. Power Supply Noise Noise Band 30kHz PIN NAMES RBIAS Description External resistance for bias current generation External reference voltage for AC Ground. Current supplied to REF2P5 Tx and Rx AC ground current sinking capability REF2P5* 0.97 MIN 12.3 NOM 12.4 MAX 12.5 UNIT K COMMENTS To create 200uA bias current. External reference voltage must be 3% accurate REF2P5 2.425 2.5 2.575 V I(REF2P5) TXANG/ RXANG 3.75uA REF2P5 8.25uA REF2P5* 1.03 V V 1mA source/sink 15/26 STLC1512 4.6 Digital Interface Logic Level Table 13. Definition of Logic Levels for Digital Control Input Pins SYMBOL VIL VIH DESCRIPTION Input low voltage Input high voltage 2.0 MIN NOM MAX 0.8 UNITS V V COMMENTS Signal from STLC1510 Signal from STLC1510 4.7 ESD and Latch Up Table 14. ESD and Latch up Parameter Electrostatic Discharge1 Latchup current Conditions 1 100 Min 2 200 Obj Max kV mA Unit <1>Test assumes standard Human body ESD model. Industry standard requirement is 1kV. 5.0 APPLICATION DIAGRAM To reduce the power consumption of the power amplifier, the two output power transistors of the power amplifier are powered by a switching power supply at the center tap of the transformer. (See Figure 7.) The switching is controlled by the digital chip (STLC1510) that senses the future signal level. The stability and offset of the power amplifier are optimized with the feedback scheme and the component values shown in this application diagram. As such, the application of the STLC1512 has to follow the topology and component values in the diagram to avoid stability and offset problems. 16/26 STLC1512 Figure 7. Application Diagram 17/26 STLC1512 Appendix A - PGA Gain Calculations The application requires some drop from the output of the hybrid balance to the input of the PGA in order to keep the signal level at an acceptable level. (see Table 5) The input is reduced by placing a resistor between the output of the hybrid balance network and PGAIN. This resistor (Rext) serves two purposes. First, it creates a resistor divider between the hybrid balance and the input. Second, it allows a capacitor to be placed across the input of the PGA to create a first order low pass filter. This further reduces the signal in long loop cases. The resistor divider is formed by the external resistor and the input impedance of the PGA. The gain from the hybrid balance to the output of the PGA is therefore given by R in put 20 log ---------------------------------- + G tab le R in put + R ex t where Gtable is the gain number given in Table , Rinput is the input impedance of the PGA given in Table Rext is the resistance placed between the hybrid balance and PGAIN. Equation can also be used to determine variations over process and temperature. To accomplish this just determine the max and min values using the input resistance variation given in Table . To convert the noise numbers in Table to line referred noise numbers use 1000 N dB = 10 log ------------ V + G + H 100 n Where Ndb is the noise on the line in dBm/Hz, Vn is the input referred noise from Table , H is the hybrid loss (9.54dB in the reference design), and G is given by R inp ut + R e xt G = 20 log ---------------------------------- R inp ut 2 18/26 STLC1512 Appendix B - Rx Path Noise Performance The following plots show the noise performance of the receive path as it is shown in Figure 7. They show the effects of different gain settings as well as typical and worst case performance of the receiver. These noise numbers are referred to the line. Figure 8. Noise for Various Gain Settings 19/26 STLC1512 Appendix C - Transmit Path Noise Performance The following plots show the noise performance of the transmit path as it is connected in Figure 7. Figure 9. Transmit Filter Noise Performance at he Filter Output (nV/Hz) 20/26 STLC1512 Figure 10. Power Amp Noise Performance at the Line (nV/Hz) 21/26 STLC1512 Figure 11. Total Transmit Path Noise Performance at the Line (nV/Hz) 22/26 STLC1512 Appendix D - Headroom Calculation for Switching The headroom for switching can be determined from the numbers in Table 4. The switching headroom is 0.70 V at low currents (i.e. while on the low supply rail) and 0.85 V at high currents (i.e. while on the high supply rail). The most difficult number to arrive at is the voltage that will appear at the pins PAOP1,2 and PAON1,2. This is a combination of the input voltage, the line impedance and the losses in the transformers. For a 100 load the maximum signal on the line will be 10.7 V. Since we are generating an active 100 output impedance the voltage on the line for any other load is given by: Zo V li ne = 2 ( 10.7 ) ---------------------- 100 + Z o (EQ D.1) where Zo is the line impedance and Vline is the voltage on the line. There are various losses in the transformers that can be modeled as resistors. To calculate the effect of these losses we must know the current through the load which is given by: V l ine I l oad = -----------Zo (EQ D.2) The loss through the line transformer can be modeled as a 2.6 resistor. There is also a drop across the two 10 reference resistors. Therefore to determine the voltage at the output of the switched transformer we have: V s wtxo ut = V line + ( 20 + 2.6 )I loa d (EQ D.3) At this point there is some additional current that flows through the hybrid balance network. This current flows through a resistance that is equivalent to 1270. Therefore the current flowing out of the switched transformer is: V swtx ou t I s wtxo ut = I loa d + ---------------------1270 (EQ D.4) The switched transformer has losses that can be modeled as a 3.6 resistor and has a 4:1 turns ratio. Therefore the voltage at the primary side of the transformer is given by: V swtx out + 3.6 ( I s wtxo ut ) V PA Ox = -------------------------------------------------------------(EQ D.5) 4 Where VPAOx is the voltage at the output pins of the power amp. This is essentially the amount of headroom required to drive a full scale signal into the desired line impedance (Zo). Equation D.1 to Equation D.5 can be combined to calculate the required headroom to drive a certain impedance. Z + 20 + 2.6 o V n Z o + 20 + 2.6 + 3.6 --------------------------------- + 1 1270 (EQ D.6) V PA Ox = ------ -------------------------------------------------------------------------------------------------- Z o + 100 2 Where VPAOx is the required headroom to drive Vn volts out onto a line with the impedance Zo. This equation can be rearranged to calculate the switching threshold. The headroom can be determined from the drop across the diode from the low supply and the low current drive capability of the amplifier given in Table (0.70V). V hea droo m = V s up ply min - 0.70 - V dio de (EQ D.7) Where Vsupplymin is the minimum value for the lower supply, Vheadroom is the headroom available on the low supply and V diode is the voltage drop across the diode when it has the appropriate amount of current flowing through it. Substituting Vheadroom in for VPAOx in Equation D.7 you can determine the allowable output voltage Vn. This can be scaled to the nominal value of 10.7V (full scale) to determine a switching threshold based on the full scale level of the signal. The headroom calculation is worst at maximum line impedance. There is also a supply rail requirement for the high (5.0V) supply which is based on being able to supply enough current to drive an 80 line impedance. This is not a trivial calculation and has been based on simulations. The possibility exists that the requirements on the minimum supply voltage may be able to be reduced in the future. 23/26 STLC1512 Appendix E - Board Issues for Heat Dissipation The internal temperature of the device must remain below 125oC. There are a number of ways to ensure that this happens. There are various combinations of maximum ambient temperature and board issues that can contribute to the junction temperature of the devices on the chip. Different layout techniques can be used to enhance the thermal coefficient of the package. The following conditions must be true to ensure reliable operation of the line driver. T am bi ent + R j ( P D ) < 125 C o (EQ E.1) Where Tambient is the maximum ambient temperature that will be experienced by the device, R j is the thermal coefficient as described below and P D is the power dissipation of the chip which is 480mW. The thermal coefficient is determined by the board layout characteristics and the rate that air is being forced across the board. The board layout is defined in 2 ways. One is a 2 layer board with signal layers on the top and bottom. The signal layer has a heat spreading copper plane that spreads from the corner pins of the chip. There are also thermal vias directly under the chip. The second layout is an 8 layer board with signal layers on the top an bottom, 4 copper lattice planes (80% 1 ounce copper) and 2 copper ground planes (solid 1 ounce copper). This layout also has a heat spreading copper plane on the signal layer and thermal vias under the die and in the copper plane. The thermal coefficients for these two different boards are given in Table 15. These coefficients are modified based on the amount of air flow over the board.. Table 15. Thermal Coefficients for Different Board Conditions Board Type 2 Layer 8 Layer Rj No Air Flow ( C/W) 87.2 54.7 o Rj 1m/s Air Flow ( C/W) 75.6 50.6 o Rj 3m/s Air Flow ( C/W) 63.6 48.0 o Rj 5m/s Air Flow (oC/W) 59.4 46.1 24/26 STLC1512 6.0 MECHANICAL SPECIFICATIONS The STLC1512 is packaged in a 48 pin 7x7x1.4mm Lowprofile Quad Flat Pack (LQFP) package. DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.45 0.05 1.35 0.17 0.09 9.00 7.00 5.50 0.50 9.00 7.00 5.50 0.60 1.00 0.75 0.018 1.40 0.22 mm TYP. MAX. 1.60 0.15 1.45 0.27 0.20 0.002 0.053 0.006 0.004 0.354 0.276 0.217 0.020 0.354 0.276 Body: 7 x 7 x 1.40mm 0.217 0.024 0.039 0.030 0.055 0.008 MIN. inch TYP. MAX. 0.063 0.006 0.057 0.010 0.008 OUTLINE AND MECHANICAL DATA TQFP48 0(min.), 3.5(typ.), 7(max.) 25/26 STLC1512 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (R) 2000 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 26/26 |
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